The invention relates to passivation layers that protect semiconductor devices from hostile environmental conditions and help control electrical properties of the outer semiconductor layers of the devices. In particular, the invention pertains to protective layers of dielectric materials with appropriate physical properties to provide means for improving the surface quality and electrical performance of a semiconductor device.
The accumulation of charge carriers within energy states along the surface of the device and within the passivation layers themselves affects device performance in undesirable ways. Passivation layers are known to provide a dual benefit of helping to protect semiconductor surfaces against environmental contamination while also reducing the density of interface traps present at the surface of the material at which charge can accumulate.
Passivation layers, however, have the drawback of possibly interfering with the operation of the device. The protection offered by the passivation layer may be defeated by problems that the layers cause during operation. Over time, however, protective passivation layers have been designed using relatively thin oxide or nitride layers, or both, that have minimized or avoided detrimental effects on the performance of the device. Often, the passivation can even improve the performance of the device.
An example of a protective passivation layer is shown in U.S. Pat. No. 5,057,897 issued to Nariani et al. on Oct. 15, 1991. The Nariani patent states that “it is generally desired to protect the exposed metal with a passivation structure. Passivation structures including an oxide layer followed by a nitride layer have proved effective at protecting the underlying structure from environmental attack.” Column 1, lines 53-57. The Nariani patent, however, is limited to protecting the device from outside elements and provides no additional control over the electro-chemical processes at work within the device itself.
More complex devices have brought forth a need for more sophisticated passivation layers. Protecting an overall device from outside elements is a worthy endeavor, but encapsulating a device with a passivation layer may not necessarily protect the device from undesired internal chemical or electrical interactions that can affect the electrical response within the device. Modern devices, therefore, require passivation layers that protect the device from chemical and electrical conditions within the device as well as protecting the device from any hostile outside environment. Simple encapsulation of certain devices with an oxide or nitride layer may be ineffective to provide sufficient environmental protection, device stability, and simultaneous optimization of performance.
Field effect transistors are typical semiconductor devices which can benefit from having a passivation layer. In a field effect transistor, a voltage applied to a control contact (called the “gate”) determines the amount of charge in a conductive channel within the device, and thereby controls the amount of current that can flow in the channel. Current generally flows between source and drain contacts located at either end of the channel.
A small input signal applied to the gate may modulate a relatively large amount of current in the channel, resulting in signal amplification if an appropriate load is presented. If the control contact is a contact directly on the surface of the semiconductor, other mobile or trapped charges on or near the surfaces adjacent to the control contact of such devices can hinder proper modulation of the conductive channel by the control voltage.
A recurring problem in achieving the proper control bias is the presence of energy states at or near the intersection of the control contact and the semiconductor body. These energy states can occur on the surface of the device and within any passivation layer covering the device. Charge carriers can accumulate in these energy states to create surface charges on the semiconductor or buried charge within the passivation layer. The charged states significantly deteriorate performance of semiconductor devices by affecting the current flow in the conducting layer below the areas adjacent to the gate. Trapping occurs when charge carriers are caught in localized energy states that are present along the surface of the semiconductor device and within surface passivation layers. Charge carriers trapped within these energy states are problematic, as they affect the overall electrical characteristics of the device. For example, since electric charges give rise to electric fields, accumulated charge carriers may cause unwanted electric fields to be present in the semiconductor structure.
Trapping can occur when the charge carriers achieve high energy levels during device operation, or may even penetrate the passivation due to the high electric fields present in the device.
Under other theories, un-terminated chemical bonds at the surface of a high frequency device with a metal contact can create charged states on the surface. See U.S. Pat. No. 6,316,793 entitled “Nitride Based Transistors on Semi-insulating Silicon Carbide Substrates” issued to Sheppard, et al. on Nov. 13, 2001. These unterminated chemical bonds may trap a portion of the carriers that would otherwise flow in the channel of a field effect transistor, such as the two dimensional electron gas of a high electron mobility transistor (HEMT). The inventors do not wish to be bound by any of the theories presented herein and provide this discussion only as background material for this specification.
Preventing the problems caused by surface charges has been a goal for some time in the field of semiconductor electronics. The solutions presented to date have largely centered on applying a passivation layer upon the surface of the devices to prevent charge accumulation along these surfaces. Passivation techniques include coating the surface of semiconductor devices with a layer of material that reduces the ability of the semiconductor surface to trap carriers injected from the metal contact or from the semiconductor material itself.
Several groups reported as early as 1994 that silicon nitride passivation in the source-gate and gate-drain region reduces the degree of current collapse. The silicon nitride layer alone, however, could not diminish current collapse completely. See Simin et al., SiO2/AlGaN/InGaN/GaN MOSDHFETs, IEEE Electron Device Letters, Volume 23, No. 8, August 2002, pages 458-460.
Other researchers showed that a thin silicon dioxide (SiO2) layer deposited on semiconductor devices reduced the density of interface traps along the surface and led to a corresponding reduction in surface charge. See Dang et al., Influence of Surface Processing and Passivation on Carrier Concentrations and Transport Properties in AlGaN/GaN Heterostructures, Journal of Applied Physics, Aug. 1, 2001, pages 1357-1360.
Experiments using silicon dioxide passivation layers have shown that semiconductor devices performed best when the silicon dioxide (SiO2) layer was positioned between the metal contact and the semiconductor material. See Khan et al., AlGaN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor, IEEE Electron Device Letters, February 2000, pages 63-65. Placing a thin SiO2 layer under a rectifying contact on a semiconductor device continued to be the focus of later research as well. See Simin et al., SiO2/AlGaN/InGaN/GaN MOSDHFETs, IEEE Electron Device Letters, Volume 23, No. 8, August 2002, pages 458-460. Simin et al. reported, however, that SiO2 layer incorporation under the gate does not affect the mechanism responsible for current collapse in these devices.
Accordingly, more effective passivation structures are needed to provide improved device performance.